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Integrated Circuit Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
FEATURES
* 2 differential 2.5V/3.3V LVPECL / ECL outputs * 1 differential PCLK, nPCLK input pair * PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Maximum output frequency: >3GHz * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input * Output skew: 5ps (typical) * Part-to-part skew: 130ps (maximum) * Propagation delay: 390ps (maximum) * Additive phase jitter, RMS: 0.06ps (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -2.375V * -40C to 85C ambient operating temperature * Available in both, Standard and RoHS/Lead-Free compliant packages
GENERAL DESCRIPTION
The ICS853011 is a low skew, high performance 1-to-2 Differential-to-2.5V/3.3V LVPECL/ HiPerClockSTM ECL Fanout Buffer and a member of the HiPerClockSTM family of High Perfor mance Clock Solutions from ICS. The ICS853011 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-par t skew characteristics make the ICS853011 ideal for those clock distribution applications demanding well defined perfor mance and repeatability.
ICS
BLOCK DIAGRAM
PCLK nPCLK Q0 nQ0 Q1 nQ1
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 Vcc PCLK nPCLK VEE
ICS853011
8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View
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Integrated Circuit Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Type Output Output Power Input Input Power Pullup/ Pulldown Pulldown Description Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Negative supply pin. Clock input. VCC/2 default when left floating. LVPECL interface levels. Clock input. Default LOW when left floating. LVPECL interface levels. Positive supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5 6 7 8 Name Q0, nQ0 Q1, nQ1 VEE nPCLK PCLK VCC
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLDOWN RVCC/2 Parameter Input Pulldown Resistor Pullup/Pulldown Resistors Test Conditions Minimum Typical 75 50 Maximum Units k k
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Integrated Circuit Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (ECL mode, VCC = 0) -0.5V to VCC + 0.5V 0.5V to VEE - 0.5V 50mA 100mA -65C to 150C 112.7C/W (0 lfpm) to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character-
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40C to +85C
istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3. 3 Maximum 3.8 25 Units V mA
TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Symbol VOH VOL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLK, nPCLK High Current Input Low Current PCLK -40C Min
2.175 1.405 150 1.2
25C Max
2.38 1.68 1200 3.3 150
85C Ma x
2.37 1.615 1200 3.3 150
Typ
2.275 1.545 800
Mi n
2.225 1.425 150 1. 2
Typ
2.295 1.52 800
Min
2.22 1.44 150 1.2
Typ
2.295 1.535 800
Max
2.365 1.63 1200 3.3 150
Units
V V V V A A A
-10 -150
-10 -150
-10
nPCLK -150 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Symbol VOH VOL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLK, nPCLK High Current PCLK Input Low Current nPCLK Min
1.375 0.605 150 1.2
-40C Typ
1.475 0.745 800
Max
1.58 0.88 1200 2.5 150
Min
1.425 0.625 150 1.2
25C Typ
1.495 0.72 800
Max
1.57 0.815 1200 2.5 150
Min
1.42 0.64 150 1.2
85C Typ
1.495 0.735 800
Max
1.565 0.83 1200 2.5 150
Units
V V V V A A A
-10 -150
-10 -150
-10 -150
For notes see above Table 3B, 3.3V LVPECL DC Characteristics.
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ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
-40C Min
-1.125 -1.895 150 VEE+1.2V
TABLE 3D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V
Symbol VOH VOL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLK, nPCLK High Current Input PCLK 25C Max
-0.92 -1.62 1200 0 150 -10 -10
85C Max
-0.93 -1.685 1200 0 150 -10
Typ
-1.025 -1.755 800
Min
-1.075 -1.875 150 VEE+1.2V
Typ
-1.005 -1.78 800
Min
-1.08 -1.86 15 0 VEE+1.2V
Typ
-1.005 -1.765 800
Max
-0.935 -1.67 1200 0 150
Units
V V V V A A A
-150 -150 -150 Low Current nPCLK Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
TABLE 4. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V
Symbol fMAX Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, Integration Range: 12KHz to 20MHz Output Rise/Fall Time 20% to 80% 70 245 5 Min
OR
VCC = 2.375 TO 3.8V; VEE = 0V
25C Max >3 375 20 130 26 0 5 Min Typ Max >3 390 20 130 0.06 25 0 80 250 100 0.06 250 275 5 Min 85C Typ Max >3 415 20 150 Units GHz ps ps ps ps ps
-40C Typ
tPD tsk(o) tsk(pp) tjit
tR/tF
0.06
odc Output Duty Cycle f 1GHz 48 50 52 48 50 52 48 50 52 % All parameters are measured at f 1.7GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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Integrated Circuit Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter
155.52MHz@12kHz to 20MHz = 0.06ps (typical)
SSB PHASE NOISE dBc/HZ
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
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ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC, VCCO
Qx
SCOPE
VCC
nPCLK
LVPECL
nQx PCLK
V
PP
Cross Points
V
CMR
VEE
V EE
-1.8V to -0.375V
OUTPUT LOAD AC TEST CIRCUIT
nQx PART 1 Qx nQy PART 2 Qy
tsk(pp)
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nPCLK
80% Clock Outputs
80% VSW I N G
PCLK nQ0, nQ1 Q0, Q1
tPD
20% tR tF
20%
OUTPUT RISE/FALL TIME
nQ0, nQ1 Q0, Q1
PROPAGATION DELAY
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
125
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
FIGURE 2A. LVPECL OUTPUT TERMINATION
853011BM
FIGURE 2B. LVPECL OUTPUT TERMINATION
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Integrated Circuit Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V 2.5V VCCO=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
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ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK
Zo = 60 Ohm 2.5V
2.5V 3.3V R3 120 SSTL Zo = 60 Ohm PCLK R4 120
R2 50
Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK
R1 120 R2 120
nPCLK
HiPerClockS PCLK/nPCLK
FIGURE 4A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY AN SSTL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 R2 84 HiPerClockS Input
Zo = 50 Ohm R5 100 C2 3.3V Zo = 50 Ohm LVDS C1
3.3V 3.3V R3 1K R4 1K PCLK
R4 125
nPCLK
HiPerClockS PC L K/n PCL K
R1 1K
R2 1K
FIGURE 4C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK
R5 100 - 200
R6 100 - 200
R1 125
R2 125
FIGURE 4E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
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ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resister can be tied from XTAL_IN to ground. CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resister can be tied from the CLK input to ground. TEST_CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resister can be tied from the TEST_CLK to ground. CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resister can be tied from CLK to ground. PCLK/nPCLK INPUT: For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1k resister can be tied from PCLK to ground. SELECT PINS: All select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. A 1k resister can be used. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVHSTL OUTPUT All unused LVHSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVDS OUTPUT All unused LVDS outputs should be terminated with 100 resister between the differential pair. LVDS - Like OUTPUT All unused LVDS outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. HCSL OUTPUT All unused HCSL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. SSTL OUTPUT All unused SSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
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ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853011. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS853011 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 25mA = 95mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.94mW = 61.88mW
Total Power_MAX (3.8V, with all outputs switching) = 95mW + 61.88mW = 156.88mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.157W * 103.3C/W = 101.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE JA
FOR
8-PIN SOIC, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT
RL
50 VCC - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
-0.935V
-V
OH_MAX
) = 0.935V
*
For logic low, VOUT = VOL_MAX = VCC_MAX - 1.67V (V
CC_MAX
-V
OL_MAX
) = 1.67V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V
OH_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.935V)/50] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853011 is: 96 Pin compatible with MC100LVEP11 and SY100EP11U
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ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
FOR
PACKAGE OUTLINE - M SUFFIX
8 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
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ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Package 8 lead SOIC 8 lead SOIC "Lead Free" 8 lead SOIC "Lead Free" 8 lead SOI Shipping Package tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS853011BM ICS853011BMT ICS853011BMLF ICS853011BMLFT Marking 853011B 853011B 853011BL 853011BL
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853011BM
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15
REV. C JULY 13, 2005
Integrated Circuit Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change 3.3V LVPECL Table - changed VOH @ 85 , from 2.295V min. to 2.22V min. and 2.33V typical to 2.295V typical. 2.5V LVPECL Table - changed VOH @ 85, from 1.495V min. to 1.42V min. and 1.53V typical to 1.495V typical. ECL Table - changed VOH @ 85, from -1.005V min. to -1.08V min. and -0.97V typical to -1.005V typical. Updated LVPECL Output Termination Diagrams. Updated LVPECL Clock Input Inteface Figure 4D. Corrected Figure 4C. Added "Lead Free" Par t/Order Number rows. AC Characteristics Table - added Additive Phase Jitter. Added Additive Phase Jitter Section. Features Section - added Lead-Free bullet. Added "Recommendations for Unused Input and Output Pins". Ordering Information Table - corrected Lead-Free marking and added LeadFree note. 9/2/03 Date
Rev
Table T3B T3C
Page 3 4 4 6 8 8
B
T3D
B C T4
C
T8
13 4 5 1 10 15
11/12/03 9/7/04
7/13/05
853011BM
www.icst.com/products/hiperclocks.html
16
REV. C JULY 13, 2005

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